The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC manufacturing are needed.
For example, as semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), are scaled down through various technology nodes, strained source/drain features (e.g., stressor regions) have been implemented to enhance carrier mobility and improve device performance. For example, in an N-type metal oxide semiconductor (NMOS) device, the channel between the source and drain region can have increased carrier mobility through tensile strain.
Although existing approaches to forming stressor regions for IC devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects. Accordingly, it is desirable to have processes that create tensile stressed channels in an efficient manner.